Job Description

Attached is the JD for reference, please ensure the participation is full and mandatory, and come up with ensure to interact with HM. Sending you the Calendar invite.

 

1. Develop and execute verification plans for complex ASIC designs 

2. Create and maintain testbenches using SystemVerilog and UVM 

3. Design and implement efficient verification environments 

4. Perform functional and formal verification of digital designs 

5. Analyze and debug design issues identified during verification 

6. Collaborate with design engineers to resolve functional discrepancies

 

Skills:

1. 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM 

2. Strong debugging, problem-solving, and analytical skills 

3. Solid understanding of digital logic design, computer architecture, and communication protocols

 

Education:

1. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field